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ICPP
1999
IEEE
15 years 11 months ago
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting
This paper presents a mesh with virtual buses as the bandwidth-efficient implementation of the mesh with multiple broadcasting on which many computational problems can be solved w...
Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-I...
HPCA
1998
IEEE
15 years 11 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 11 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
RTAS
1997
IEEE
15 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
SIGCOMM
1996
ACM
15 years 11 months ago
Receiver-Driven Layered Multicast
State of the art, real-time, rate-adaptive, multimedia applications adjust their transmission rate to match the available network capacity. Unfortunately, this source-based rate-a...
Steven McCanne, Van Jacobson, Martin Vetterli