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ISESE
2003
IEEE
15 years 11 months ago
An Experimental Evaluation of Inspection and Testing for Detection of Design Faults
The two most common strategies for verification and validation, inspection and testing, are in a controlled experiment evaluated in terms of their fault detection capabilities. Th...
Carina Andersson, Thomas Thelin, Per Runeson, Nina...
ICCAD
2000
IEEE
97views Hardware» more  ICCAD 2000»
15 years 10 months ago
Error Catch and Analysis for Semiconductor Memories Using March Tests
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...
Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-L...
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
15 years 10 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...
COMPSAC
2010
IEEE
15 years 4 months ago
Minimising the Preparation Cost of Runtime Testing Based on Testability Metrics
Abstract--Test cost minimisation approaches have traditionally been devoted to minimising "execution costs", while maximising coverage or reliability. However, in a runti...
Alberto González-Sanchez, Éric Piel,...
ECCC
2011
185views ECommerce» more  ECCC 2011»
15 years 1 months ago
Property Testing Lower Bounds via Communication Complexity
We develop a new technique for proving lower bounds in property testing, by showing a strong connection between testing and communication complexity. We give a simple scheme for r...
Eric Blais, Joshua Brody, Kevin Matulef