1321 search results - page 210 / 265 » Subtyping in Logical Form |
174
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ASYNC
2005
IEEE
15 years 12 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
138
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DATE
2005
IEEE
15 years 12 months ago
2005
IEEE
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...
158
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ADBIS
2005
Springer
15 years 11 months ago
2005
Springer
The current period of IT development is characterized by an explosive growth of diverse information representation languages. Applying integration and composition of heterogeneous ...
165
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ECSQARU
2005
Springer
15 years 11 months ago
2005
Springer
Conditional deduction in binary logic basically consists of deriving new statements from an existing set of statements and conditional rules. Modus Ponens, which is the classical e...
166
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IMC
2004
ACM
15 years 11 months ago
2004
ACM
The capacity of today's network links, along with the heterogeneity of their traffic, is rapidly growing, more than the workstation’s processing power. This makes the task ...