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ICDE
2005
IEEE
144views Database» more  ICDE 2005»
16 years 8 months ago
ViteX: A Streaming XPath Processing System
We present ViteX, an XPath processing system on XML streams with polynomial time complexity. ViteX uses a polynomial-space data structure to encode an exponential number of patter...
Yi Chen, Susan B. Davidson, Yifeng Zheng
RECOMB
2002
Springer
16 years 7 months ago
Simulating a Coalescent Process with Recombination and Ascertainment
A new method is presented for use in simulating samples of disease and normal chromosomes bearing multiple linked genetic markers under a neutral model of mutation, genetic drift, ...
Ying Wang, Bruce Rannala
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
16 years 24 days ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speciļ¬...
Robert L. Bocchino Jr., Vikram S. Adve
SIGCOMM
2009
ACM
16 years 1 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
16 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...