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DAC
2009
ACM
16 years 24 days ago
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
CODES
2009
IEEE
16 years 23 days ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
ISQED
2007
IEEE
120views Hardware» more  ISQED 2007»
16 years 9 days ago
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, ...
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
16 years 2 days ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram
VLSID
2005
IEEE
105views VLSI» more  VLSID 2005»
15 years 11 months ago
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
R. Manimegalai, E. Siva Soumya, V. Muralidharan, B...