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ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
16 years 1 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
16 years 23 days ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
16 years 9 days ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
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ICPADS
2005
IEEE
16 years 8 days ago
Efficient Distributed QoS Routing Protocol for MPLS Networks
- This paper proposes a new distributed QoS routing protocol, called Efficient Distributed QoS Routing (EDQR), for MPLS networks. The path searching algorithm of EDQR considers an ...
Man-Ching Yuen, Weijia Jia, Chi-Chung Cheung
PLDI
2003
ACM
15 years 12 months ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume