Sciweavers

306 search results - page 33 / 62
» Statistical Delay Modeling in Logic Design and Synthesis
Sort
View
TCAD
2010
107views more  TCAD 2010»
15 years 21 days ago
Evaluating Statistical Power Optimization
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this ...
Jason Cong, Puneet Gupta, John Lee
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
15 years 11 months ago
Digital statistical analysis using VHDL
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
Manfred Dietrich, Uwe Eichler, Joachim Haase
ASPDAC
2009
ACM
111views Hardware» more  ASPDAC 2009»
16 years 15 days ago
A UML-based approach for heterogeneous IP integration
- With increasing availability of predefined IP (Intellectual Properties) blocks and inexpensive microprocessors, embedded system designers are faced with more design choices than ...
Zhenxin Sun, Weng-Fai Wong
ICS
2004
Tsinghua U.
15 years 11 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
TWC
2008
127views more  TWC 2008»
15 years 5 months ago
Energy-Delay Analysis of MAC Protocols in Wireless Networks
In this paper the tradeoff between energy and delay for wireless networks is studied. A network using a request-to-send (RTS) and clear-to-send (CTS) type medium access control (M...
Shih Yu Chang, Wayne E. Stark, Achilleas Anastasop...