306 search results - page 30 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
158
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GPCE
2008
Springer
15 years 7 months ago
2008
Springer
A user interface, such as a dialog, assists a user in synthesising a set of values, typically parameters for a command object. Code for “command parameter synthesis” is usuall...
152
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ICCAD
1998
IEEE
15 years 10 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
161
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RTAS
2005
IEEE
15 years 11 months ago
2005
IEEE
The increasing popularity of high-volume performancecritical Internet applications calls for a scalable server design that allows meeting individual response-time guarantees. Cons...
161
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ISQED
2007
IEEE
16 years 7 days ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
136
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ASPDAC
2009
ACM
16 years 15 days ago
2009
ACM
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this...