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DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 10 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
166
Voted
EDCC
2006
Springer
15 years 10 months ago
Automatically Finding and Patching Bad Error Handling
Bad error handling is the cause of many service outages. We address this problem by a novel approach to detect and patch bad error handling automatically. Our approach uses error ...
Martin Süßkraut, Christof Fetzer
EUROGP
2008
Springer
112views Optimization» more  EUROGP 2008»
15 years 8 months ago
Evolvability Via Modularity-Induced Mutational Focussing
Abstract. This work postulates a mechanism by which random genotypic variation is directed towards favourable phenotypic variation. Evolvability is a poorly understood concept at p...
Richard M. Downing
DLOG
2006
15 years 8 months ago
SHIN ABox Reduction
We propose a technique to make consistency detection scalable for large Aboxes in secondary storage. We use static analysis of knowledge representation with summarization techniqu...
Achille Fokoue, Aaron Kershenbaum, Li Ma
FIW
2000
147views Communications» more  FIW 2000»
15 years 8 months ago
Formalising the Chisel Feature Notation
The CHISEL notation was developed by Bellcore as an informal graphical notation for describing telecomms services and features. CRESS (CHISEL Representation Employing Systematic S...
Kenneth J. Turner