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» State machine models of timing and circuit design
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ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
16 years 1 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
FMICS
2007
Springer
16 years 10 days ago
Machine Checked Formal Proof of a Scheduling Protocol for Smartcard Personalization
Using PVS (Prototype Verification System), we prove that an industry designed scheduler for a smartcard personalization machine is safe and optimal. This scheduler has previously ...
Leonard Lensink, Sjaak Smetsers, Marko C. J. D. va...
FORMATS
2006
Springer
15 years 9 months ago
On the Computational Power of Timed Differentiable Petri Nets
Abstract. Well-known hierarchies discriminate between the computational power of discrete time and space dynamical systems. A contrario the situation is more confused for dynamical...
Serge Haddad, Laura Recalde, Manuel Silva
TPDS
2008
76views more  TPDS 2008»
15 years 6 months ago
How to Choose a Timing Model
When employing a consensus algorithm for state machine replication, should one optimize for the case that all communication links are usually timely, or for fewer timely links? Do...
Idit Keidar, Alexander Shraer
DSN
2007
IEEE
16 years 15 days ago
How to Choose a Timing Model?
When employing a consensus algorithm for state machine replication, should one optimize for the case that all communication links are usually timely, or for fewer timely links? Do...
Idit Keidar, Alexander Shraer