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» State, Event, Time and Diagram in System Modeling
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IPPS
2006
IEEE
16 years 5 days ago
Timed automata based analysis of embedded system architectures
We show that timed automata can be used to model and to analyze timeliness properties of embedded system architectures. Using a case study inspired by industrial practice, we pres...
Martijn Hendriks, Marcel Verhoef
CAV
2012
Springer
251views Hardware» more  CAV 2012»
13 years 8 months ago
A Model Checker for Hierarchical Probabilistic Real-Time Systems
Real-life systems are usually hard to control, due to their complicated structures, quantitative time factors and even stochastic behaviors. In this work, we present a model checke...
Songzheng Song, Jun Sun 0001, Yang Liu 0003, Jin S...
CAV
1993
Springer
127views Hardware» more  CAV 1993»
15 years 10 months ago
Symbolic Equivalence Checking
Abstract. We describe the implementation, within ALDEBARAN of an algorithmic method allowing the generation of a minimal labeled transition rom an abstract model ; this minimality ...
Jean-Claude Fernandez, Alain Kerbrat, Laurent Moun...
ENTCS
2006
112views more  ENTCS 2006»
15 years 6 months ago
Patterns for Timed Property Specifications
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...
Volker Gruhn, Ralf Laue
WSC
2007
15 years 8 months ago
Statistical analysis of simulation output: state of the art
This paper reviews statistical methods for analyzing output data from computer simulations. Specifically, it focuses on the estimation of steady-state system parameters. The esti...
Christos Alexopoulos