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VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
16 years 7 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
TACAS
2010
Springer
221views Algorithms» more  TACAS 2010»
16 years 1 months ago
Trace-Based Symbolic Analysis for Atomicity Violations
Abstract. We propose a symbolic algorithm to accurately predict atomicity violations by analyzing a concrete execution trace of a concurrent program. We use both the execution trac...
Chao Wang, Rhishikesh Limaye, Malay K. Ganai, Aart...
TASE
2009
IEEE
16 years 1 months ago
Fault-Based Test Case Generation for Component Connectors
The complex interactions appearing in service-oriented computing make coordination a key concern in serviceoriented systems. In this paper, we present a fault-based method to gene...
Bernhard K. Aichernig, Farhad Arbab, Lacramioara A...
ADBIS
2009
Springer
151views Database» more  ADBIS 2009»
16 years 1 months ago
Rule-Based Management of Schema Changes at ETL Sources
In this paper, we visit the problem of the management of inconsistencies emerging on ETL processes as results of evolution operations g at their sources. We abstract Extract-Transf...
George Papastefanatos, Panos Vassiliadis, Alkis Si...
IWANN
2009
Springer
16 years 1 months ago
Optimising Machine-Learning-Based Fault Prediction in Foundry Production
Abstract. Microshrinkages are known as probably the most difficult defects to avoid in high-precision foundry. The presence of this failure renders the casting invalid, with the su...
Igor Santos, Javier Nieves, Yoseba K. Penya, Pablo...