1945 search results - page 259 / 389 » Speeding up Serpent |
154
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DATE
2005
IEEE
16 years 14 hour ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
173
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EUROMICRO
2005
IEEE
16 years 11 hour ago
2005
IEEE
Code revision of a leading telecom product was performed, combining manual audit and static analysis tools. On average, one exploitable vulnerability was found for every 4000 line...
157
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FCCM
2005
IEEE
16 years 10 hour ago
2005
IEEE
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructu...
182
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HPCA
2005
IEEE
16 years 8 hour ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
181
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HPCA
2005
IEEE
16 years 8 hour ago
2005
IEEE
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...