1942 search results - page 39 / 389 » Speeding Up XTR |
161
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ERSA
2003
15 years 7 months ago
2003
The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multipl...
154
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ISCAS
2007
IEEE
16 years 11 days ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
152
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HIPEAC
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
149
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ICCV
2009
IEEE
16 years 11 months ago
2009
IEEE
Prominent feature point descriptors such as SIFT and
SURF allow reliable real-time matching but at a compu-
tational cost that limits the number of points that can be
handled on...
131
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MASCOTS
2004
15 years 7 months ago
2004
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleSc...