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MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
15 years 10 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 10 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 9 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
HPCA
2011
IEEE
14 years 9 months ago
Calvin: Deterministic or not? Free will to choose
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
Derek Hower, Polina Dudnik, Mark D. Hill, David A....
CSL
2005
Springer
15 years 11 months ago
Distributed Control Flow with Classical Modal Logic
In previous work we presented a foundational calculus for spatially distributed computing based on intuitionistic modal logic. With the modalities P and Q we were able to capture t...
Tom Murphy VII, Karl Crary, Robert Harper