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ISCA
1997
IEEE
104views Hardware» more  ISCA 1997»
15 years 10 months ago
Complexity-Effective Superscalar Processors
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
Subbarao Palacharla, Norman P. Jouppi, James E. Sm...
TARK
2005
Springer
15 years 11 months ago
Logical omniscience and common knowledge: WHAT do we know and what do WE know?
: Two difficult issues for the logic of knowledge have been logical omniscience and common knowledge. Our existing logics of knowledge based on Kripke structures seem to justify lo...
Rohit Parikh
PACS
2004
Springer
115views Hardware» more  PACS 2004»
15 years 11 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
IEEEPACT
2005
IEEE
15 years 11 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
MICRO
1994
IEEE
123views Hardware» more  MICRO 1994»
15 years 10 months ago
The effects of predicated execution on branch prediction
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
Gary S. Tyson