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DAC
2001
ACM
16 years 7 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
DAC
2005
ACM
16 years 7 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
SAS
2009
Springer
147views Formal Methods» more  SAS 2009»
16 years 6 months ago
Polymorphic Fractional Capabilities
Abstract. The capability calculus is a framework for statically reasoning about program resources such as deallocatable memory regions. Fractional capabilities, originally proposed...
Hirotoshi Yasuoka, Tachio Terauchi
HIPEAC
2010
Springer
16 years 3 months ago
Scalable Shared-Cache Management by Containing Thrashing Workloads
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...
Yuejian Xie, Gabriel H. Loh
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
16 years 3 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...