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DATE
2007
IEEE
128views Hardware» more  DATE 2007»
16 years 1 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
196
Voted
ICC
2007
IEEE
130views Communications» more  ICC 2007»
16 years 1 months ago
Queuing with Adaptive Modulation over MIMO Wireless Links for Deadline Constrained Traffic: Cross-Layer Analysis and Design
In this paper, we consider a deadline constrained traffic and analyze the joint effects of packet queuing and adaptive modulation (AM) for packet transmission in MIMO systems. We p...
Jalil S. Harsini, Farshad Lahouti
NCA
2007
IEEE
16 years 1 months ago
A Topological Analysis of Monitor Placement
The Internet is an extremely complex system, and it is essential that we be able to make accurate measurements in order to understand its underlying behavior or to detect improper...
Alden W. Jackson, Walter C. Milliken, Cesar A. San...
IEEEARES
2006
IEEE
16 years 24 days ago
Identifying Intrusions in Computer Networks with Principal Component Analysis
Most current anomaly Intrusion Detection Systems (IDSs) detect computer network behavior as normal or abnormal but cannot identify the type of attacks. Moreover, most current intr...
Wei Wang, Roberto Battiti
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
16 years 23 days ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...