354 search results - page 25 / 71 » Sorting networks on FPGAs |
142
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
151
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FPL
2000
Springer
15 years 9 months ago
2000
Springer
Following the simple Programmable Logic Device (SPLD) and Field Programmable Gate Array (FPGA) generations a third generation of programmable logic technologies is now reaching the...
176
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ANOR
2010
15 years 3 months ago
2010
We present a methodology to automatically generate an online job scheduling method for a custom-made objective and real workloads. The scheduling problem comprises independent para...
146
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ISMVL
1994
IEEE
15 years 10 months ago
1994
IEEE
The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks...
149
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ARC
2008
Springer
15 years 8 months ago
2008
Springer
Abstract. In this paper we present a networked lightweight and partially reconfigurable platform assisted by a remote bitstreams server. We propose a software and hardware architec...