1406 search results - page 110 / 282 » Software trace cache |
147
click to vote
DATE
2009
IEEE
16 years 29 days ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
160
click to vote
CGO
2007
IEEE
16 years 17 days ago
2007
IEEE
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...
135
click to vote
CASES
2001
ACM
15 years 10 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
183
click to vote
IWPC
2002
IEEE
15 years 11 months ago
2002
IEEE
When we try to debug or to comprehend a large program, it is important to separate suspicious program portions from the overall source program. Program slicing is a promising tech...
201
click to vote
CASES
2007
ACM
15 years 10 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...