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EUROMICRO
1998
IEEE
15 years 11 months ago
SMP PCs: A Case Study on Cluster Computing
As commodity microprocessors and networks reach performance levels comparable to those used in massively parallel processors, clusters of symmetric multiprocessors are starting to...
Antônio Augusto Fröhlich, Wolfgang Schr...
ICPP
1996
IEEE
15 years 11 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
ESEM
2007
ACM
15 years 10 months ago
The Effects of Over and Under Sampling on Fault-prone Module Detection
The goal of this paper is to improve the prediction performance of fault-prone module prediction models (fault-proneness models) by employing over/under sampling methods, which ar...
Yasutaka Kamei, Akito Monden, Shinsuke Matsumoto, ...
CODES
2004
IEEE
15 years 10 months ago
Optimizing the memory bandwidth with loop fusion
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
Paul Marchal, José Ignacio Gómez, Fr...
CIDR
2007
173views Algorithms» more  CIDR 2007»
15 years 8 months ago
Database Servers on Chip Multiprocessors: Limitations and Opportunities
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson...