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POPL
2010
ACM
16 years 4 months ago
A simple, verified validator for software pipelining
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
Jean-Baptiste Tristan, Xavier Leroy
CGO
2009
IEEE
16 years 1 months ago
Reducing Memory Ordering Overheads in Software Transactional Memory
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total St...
Michael F. Spear, Maged M. Michael, Michael L. Sco...
SEAA
2008
IEEE
16 years 1 months ago
A Case Study in Software Product Lines - The Case of the Mobile Game Domain
Software Product Lines (SPL) processes are gradually being adopted by many companies in several domains. A particular domain where the adoption of such processes may bring relevan...
Leandro Marques Nascimento, Eduardo Santana de Alm...
IEEEPACT
2007
IEEE
16 years 28 days ago
Unified Architectural Support for Soft-Error Protection or Software Bug Detection
In this paper we propose a unified architectural support that can be used flexibly for either soft-error protection or software bug detection. Our approach is based on dynamically...
Martin Dimitrov, Huiyang Zhou
ISPW
2007
IEEE
16 years 27 days ago
The Economic Impact of Software Process Variations
The economic benefit of a certain development process or particular activity is usually unknown and indeed hard to predict. However, the cost-effectiveness of process improvement...
Florian Deissenboeck, Markus Pizka