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PPOPP
2009
ACM
16 years 7 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader
HPCA
2008
IEEE
16 years 7 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...
HPCA
2007
IEEE
16 years 7 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
OSDI
2002
ACM
16 years 7 months ago
Optimizing the Migration of Virtual Computers
This paper shows how to quickly move the state of a running computer across a network, including the state in its disks, memory, CPU registers, and I/O devices. We call this state...
Constantine P. Sapuntzakis, Ramesh Chandra, Ben Pf...
POPL
2010
ACM
16 years 4 months ago
Higher-Order Multi-Parameter Tree Transducers and Recursion Schemes for Program Verification
We introduce higher-order, multi-parameter, tree transducers (HMTTs, for short), which are kinds of higher-order tree transducers that take input trees and output a (possibly infi...
Naoki Kobayashi, Naoshi Tabuchi, Hiroshi Unno
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