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ISPASS
2009
IEEE
16 years 1 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
VEE
2009
ACM
146views Virtualization» more  VEE 2009»
16 years 1 months ago
Demystifying magic: high-level low-level programming
r of high-level languages lies in their abstraction over hardware and software complexity, leading to greater security, better reliability, and lower development costs. However, o...
Daniel Frampton, Stephen M. Blackburn, Perry Cheng...
HIPEAC
2009
Springer
16 years 1 months ago
Collective Optimization
Abstract. Iterative compilation is an efficient approach to optimize programs on rapidly evolving hardware, but it is still only scarcely used in practice due to a necessity to gat...
Grigori Fursin, Olivier Temam
LCTRTS
2009
Springer
16 years 1 months ago
Push-assisted migration of real-time tasks in multi-core processors
Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflexion of contemporary embedded applications posing steadily incre...
Abhik Sarkar, Frank Mueller, Harini Ramaprasad, Si...
LCTRTS
2009
Springer
16 years 1 months ago
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
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