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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 10 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
EMSOFT
2010
Springer
15 years 4 months ago
Nucleos: a runtime system for ultra-compact wireless sensor nodes
Nucleos is a new runtime system for ultra-lightweight embedded systems. Central to Nucleos is a dispatcher based on the concept of e threaded code, which enables layers of abstrac...
Jiwon Hahn, Pai H. Chou
DAC
2003
ACM
16 years 7 months ago
Automated synthesis of efficient binary decoders for retargetable software toolkits
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
Wei Qin, Sharad Malik
CODES
1999
IEEE
15 years 10 months ago
System synthesis utilizing a layered functional model
We propose a system synthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is...
Ingo Sander, Axel Jantsch
PADS
2003
ACM
15 years 11 months ago
Parallel Network Simulation under Distributed Genesis
We describe two major developments in the General Network Simulation Integration System (Genesis): the support for BGP protocol in large network simulations and distribution of th...
Boleslaw K. Szymanski, Yu Liu, Rashim Gupta