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ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 10 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
AFRICACRYPT
2010
Springer
15 years 9 months ago
Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator
Abstract. This article investigates the relevance of the theoretical framework on profiled side-channel attacks presented by F.-X. Standaert et al. at Eurocrypt 2009. The analyses ...
M. Abdelaziz Elaabid, Sylvain Guilley
ASPLOS
2010
ACM
15 years 9 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
DEBS
2010
ACM
15 years 9 months ago
Workload characterization for operator-based distributed stream processing applications
Operator-based programming languages provide an effective development model for large scale stream processing applications. A stream processing application consists of many runtim...
Xiaolan J. Zhang, Sujay Parekh, Bugra Gedik, Henri...
WSC
2008
15 years 8 months ago
Introducing age-based parameters into simulations of crowd dymanics
Very few crowds consist of individuals who are exactly the same. Defining variables, such as age, and how they affect an individual's movement, could increase realism in simu...
D. J. Kaup, Thomas L. Clarke, Rex Oleson, Linda C....
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