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LCTRTS
1999
Springer
15 years 10 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
ASPLOS
1998
ACM
15 years 10 months ago
Data Speculation Support for a Chip Multiprocessor
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
Lance Hammond, Mark Willey, Kunle Olukotun
IATA
1998
Springer
15 years 10 months ago
Agent-Based Schemes for Plug-And-Play Network Components
In this paper, we present several approaches to making the process of configuring network devices easier than is currently the case. Configuring a device requires that a number of ...
Andrzej Bieszczad, Syed Kamran Raza, Bernard Pagur...
EUROMICRO
1997
IEEE
15 years 10 months ago
What's ahead in computer design?
CMOS technology should, over the next few years, reach lithography of under 0.1¡ . This provides a die area improvement of a factor of 10 over today’s technology. What is the b...
Michael J. Flynn
LCTRTS
1998
Springer
15 years 10 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström