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ASPDAC
2004
ACM
119views Hardware» more  ASPDAC 2004»
15 years 11 months ago
A fast congestion estimator for routing with bounded detours
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...
Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang
VTS
1996
IEEE
74views Hardware» more  VTS 1996»
15 years 10 months ago
An unexpected factor in testing for CMOS opens: the die surface
In this paper, we for the rst time present experimental evidence that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a o...
Haluk Konuk, F. Joel Ferguson
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 3 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
EUROPAR
2007
Springer
16 years 11 days ago
A First Step Towards Automatically Building Network Representations
To fully harness Grids, users or middlewares must have some knowledge on the topology of the platform interconnection network. As such knowledge is usually not available, one must ...
Lionel Eyraud-Dubois, Arnaud Legrand, Martin Quins...
WCRE
2006
IEEE
16 years 6 days ago
An Orchestrated Multi-view Software Architecture Reconstruction Environment
Most approaches in reverse engineering literature generate a single view of a software system that restricts the scope of the reconstruction process. We propose an orchestrated se...
Kamran Sartipi, Nima Dezhkam, Hossein Safyallah