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ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
16 years 7 days ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
HICSS
2003
IEEE
130views Biometrics» more  HICSS 2003»
15 years 12 months ago
Estimating the Actual Cost of Transmission System Congestion
This paper describes a methodology that could be used by a utility to estimate the actual cost of congestion on its transmission system using limited, non-state estimator data. Th...
Thomas J. Overbye
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
15 years 11 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
209
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HPCS
2002
IEEE
15 years 11 months ago
MetaGrid: A Scalable Framework for Wide-Area Service Deployment and Management
This paper presents a novel architecture called the MetaGrid based on Grid computing concepts for resource provisioning for wide-area network-enabled applications. Resource provis...
Muthucumaru Maheswaran, Balasubramaneyam Maniymara...
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
15 years 11 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan