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NOCS
2009
IEEE
16 years 1 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...
IJCNN
2008
IEEE
16 years 1 months ago
Wafer-scale integration of analog neural networks
Abstract— This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time a...
Johannes Schemmel, Johannes Fieres, Karlheinz Meie...
ESTIMEDIA
2007
Springer
16 years 25 days ago
Network Calculus Applied to Verification of Memory Access Performance in SoCs
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes t...
Tomas Henriksson, Pieter van der Wolf, Axel Jantsc...
ASPLOS
2006
ACM
16 years 19 days ago
Tartan: evaluating spatial computation for whole program execution
Spatial Computing (SC) has been shown to be an energy-efficient model for implementing program kernels. In this paper we explore the feasibility of using SC for more than small k...
Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea...
ICDCS
2005
IEEE
16 years 8 days ago
FraNtiC: A Fractal Geometric Framework for Mesh-Based Wireless Access Networks
The design of the access networks of next generation broadband wireless systems requires special attention in the light of changing network characteristics. In this paper, we pres...
Samik Ghosh, Kalyan Basu, Sajal K. Das