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DAC
2004
ACM
16 years 7 months ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
16 years 3 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
Premkishore Shivakumar, Stephen W. Keckler, Charle...
STOC
2004
ACM
129views Algorithms» more  STOC 2004»
16 years 6 months ago
Sorting and searching in the presence of memory faults (without redundancy)
We investigate the design of algorithms resilient to memory faults, i.e., algorithms that, despite the corruption of some memory values during their execution, are able to produce...
Irene Finocchi, Giuseppe F. Italiano
DSN
2008
IEEE
16 years 1 months ago
Coverage of a microarchitecture-level fault check regimen in a superscalar processor
Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approac...
Vimal K. Reddy, Eric Rotenberg
ICN
2005
Springer
16 years 2 days ago
Fault Free Shortest Path Routing on the de Bruijn Networks
It is shown that the de Bruijn graph (dBG) can be used as an architecture for interconnection networks and a suitable structure for parallel computation. Recent works have classiï¬...
Ngoc Chi Nguyen, Vo Dinh Minh Nhat, Sungyoung Lee