Sciweavers

2498 search results - page 209 / 500
» Software Fault Tolerance
Sort
View
ICSE
2003
IEEE-ACM
15 years 11 months ago
An Analysis of the Fault Correction Process in a Large-Scale SDL Production Model
Improvements in the software development process depend on our ability to collect and analyze data drawn from various phases of the development life cycle. Our design metrics rese...
Dolores M. Zage, Wayne M. Zage
HASE
1998
IEEE
15 years 10 months ago
Combining Various Solution Techniques for Dynamic Fault Tree Analysis of Computer Systems
Fault trees provide a graphical and logical framework for analyzing the reliability of systems. A fault tree provides a conceptually simple modeling framework to represent the sys...
Ragavan Manian, Joanne Bechta Dugan, David Coppit,...
EMSOFT
2011
Springer
14 years 6 months ago
From boolean to quantitative synthesis
Motivated by improvements in constraint-solving technology and by the increase of routinely available computational power, partial-program synthesis is emerging as an effective a...
Pavol Cerný, Thomas A. Henzinger
ICIP
2006
IEEE
16 years 8 months ago
Computation Error Tolerance in Motion Estimation Algorithms
In this paper we study the computation error tolerance properties of motion estimation algorithms. We are motivated by two scenarios where hardware systems may introduce computati...
Hye-Yeon Cheong, In Suk Chong, Antonio Ortega
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
16 years 23 days ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...