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ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
16 years 2 days ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
DFT
1994
IEEE
121views VLSI» more  DFT 1994»
15 years 10 months ago
Reconfiguration in 3D Meshes
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
Anuj Chandra, Rami G. Melhem
ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
16 years 3 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori
DATE
2010
IEEE
111views Hardware» more  DATE 2010»
15 years 11 months ago
Instruction precomputation with memoization for fault detection
—Fault tolerance (FT) has become a major concern in computing systems. Instruction duplication has been proposed to verify application execution at run time. Two techniques, inst...
Demid Borodin, Ben H. H. Juurlink
ETS
2006
IEEE
122views Hardware» more  ETS 2006»
15 years 10 months ago
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics
Online repair through reconfiguration is a particularly advantageous approach in the nanoelectronic environment since reconfigurability is naturally supported by the devices. Howe...
Wenjing Rao, Alex Orailoglu, Ramesh Karri