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186
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CGO
2008
IEEE
16 years 1 months ago
2008
IEEE
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
171
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CGO
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
173
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ISPASS
2008
IEEE
16 years 1 months ago
2008
IEEE
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
169
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ISPASS
2008
IEEE
16 years 1 months ago
2008
IEEE
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
249
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ISPASS
2008
IEEE
2008
IEEE
An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory
16 years 1 months ago
Transactional memory (TM) is a scalable and concurrent way to build atomic sections. One aspect of TM that remains unclear is how side-effecting operations – that is, those whic...