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FMCAD
2000
Springer
15 years 10 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
ICSE
2009
IEEE-ACM
16 years 7 months ago
Automatically finding patches using genetic programming
Automatic repair of programs has been a longstanding goal in software engineering, yet debugging remains a largely manual process. We introduce a fully automated method for locati...
Westley Weimer, ThanhVu Nguyen, Claire Le Goues, S...
DAC
1999
ACM
16 years 7 months ago
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
ICSE
2007
IEEE-ACM
16 years 6 months ago
On Accurate Automatic Verification of Publish-Subscribe Architectures
The paper presents a novel approach based on Bogor for the accurate verification of applications based on PublishSubscribe infrastructures. Previous efforts adopted standard model...
Luciano Baresi, Carlo Ghezzi, Luca Mottola
ASWEC
2007
IEEE
16 years 26 days ago
Formal Validation of Hierarchical State Machines against Expectations
This paper explains some analyses that can be performed on a hierarchical finite state machine to validate that it performs as intended. Such a hierarchical state machine has tra...
Ian Toyn, Andy Galloway