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JSS
2006
104views more  JSS 2006»
15 years 6 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
TIFS
2008
142views more  TIFS 2008»
15 years 6 months ago
An FPGA-Based Network Intrusion Detection Architecture
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...
INTEGRATION
2008
127views more  INTEGRATION 2008»
15 years 5 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
ICASSP
2010
IEEE
15 years 4 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Althou...
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija...
DMIN
2009
180views Data Mining» more  DMIN 2009»
15 years 4 months ago
APHID: A Practical Architecture for High-Performance, Privacy-Preserving Data Mining
While the emerging field of privacy preserving data mining (PPDM) will enable many new data mining applications, it suffers from several practical difficulties. PPDM algorithms are...
Jimmy Secretan, Anna Koufakou, Michael Georgiopoul...