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HIPEAC
2009
Springer
16 years 1 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
16 years 1 months ago
A self-adaptive system architecture to address transistor aging
—As semiconductor manufacturing enters advanced nanometer design paradigm, aging and device wear-out related degradation is becoming a major concern. Negative Bias Temperature In...
Omer Khan, Sandip Kundu
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
16 years 25 days ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
CODES
2005
IEEE
16 years 13 days ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
HIPEAC
2005
Springer
16 years 10 days ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...