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FPL
2003
Springer
81views Hardware» more  FPL 2003»
15 years 12 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
ISCAS
1999
IEEE
113views Hardware» more  ISCAS 1999»
15 years 11 months ago
Energy efficient software through dynamic voltage scheduling
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
Gangadhar Konduri, James Goodman, Anantha Chandrak...
ISSS
1997
IEEE
83views Hardware» more  ISSS 1997»
15 years 11 months ago
A Scheduling and Pipelining Algorithm for Hardware/Software Systems
Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks...
Smita Bakshi, Daniel Gajski
HICSS
1996
IEEE
111views Biometrics» more  HICSS 1996»
15 years 10 months ago
Improving Software Pipelining with Unroll-and-Jam
To take advantage of recent architectural improvements in microprocessors, advanced compiler optimizations such as software pipelining have been developed 1, 2, 3, 4]. Unfortunate...
Steve Carr, Chen Ding, Philip H. Sweany
HPCA
1996
IEEE
15 years 10 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...