A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
This paper will discuss high performance clustering from a series of critical topics: architectural design, system software infrastructure, and programming environment. This will ...
David A. Bader, Arthur B. Maccabe, Jason R. Mastal...
This paper proposes MISSA, a novel middleware to facilitate the development and provision of stream-based services in emerging pervasive environments. The streambased services util...
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
Maturity models are a well-known instrument to support the improvement of functional domains in IS, like software development or testing. While maturity models may share a common s...
Marlies van Steenbergen, Rik Bos, Sjaak Brinkkempe...