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CODES
2010
IEEE
15 years 4 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
PVM
2001
Springer
15 years 11 months ago
An Architecture for a Multi-threaded Harness Kernel
Abstract. Harness is a reconÞgurable, heterogeneous distributed metacomputing framework for the dynamic conÞguration of distributed virtual machines, through the use of parallel ...
Wael R. Elwasif, David E. Bernholdt, James Arthur ...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
16 years 1 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...
LCPC
2007
Springer
16 years 28 days ago
Revisiting SIMD Programming
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft,...
CASES
2007
ACM
15 years 10 months ago
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of micr...
Greg Hoover, Forrest Brewer, Timothy Sherwood