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ISPASS
2010
IEEE
16 years 1 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 3 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
FPT
2005
IEEE
142views Hardware» more  FPT 2005»
16 years 14 days ago
Custom Hardware Architectures for Posture Analysis
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
M. P. T. Juvonen, José Gabriel F. Coutinho,...
FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
16 years 1 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
CASES
2006
ACM
15 years 10 months ago
State space reconfigurability: an implementation architecture for self modifying finite automata
Many embedded systems exhibit temporally and behaviorally disjoint behavior slices. When such behaviors are captured by state machines, the current design flow will capture it as ...
Ka-Ming Keung, Akhilesh Tyagi