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IFIPPACT
1994
15 years 8 months ago
Microcode Generation for Flexible Parallel Target Architectures
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope ...
Rainer Leupers, Wolfgang Schenk, Peter Marwedel
AHS
2007
IEEE
222views Hardware» more  AHS 2007»
15 years 7 months ago
Programmable Analog VLSI Architecture Based upon Event Coding
Abstract— A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array...
Thomas Jacob Koickal, Alister Hamilton, Luiz C. P....
CORR
2010
Springer
88views Education» more  CORR 2010»
15 years 7 months ago
A fuzzified BRAIN algorithm for learning DNF from incomplete data
Aim of this paper is to address the problem of learning Boolean functions from training data with missing values. We present an extension of the BRAIN algorithm, called U-BRAIN (U...
Salvatore Rampone, Ciro Russo
156
Voted
ICRA
2010
IEEE
143views Robotics» more  ICRA 2010»
15 years 4 months ago
Tremor attenuation using FES-based joint stiffness control
In this paper, a strategy to attenuate tremor based on co-contraction of antagonist muscles using Functional Electrical Stimulation (FES) is fully presented. Both methods to track ...
Antônio Padilha Lanari Bo, Philippe Poignet
WWW
2008
ACM
16 years 7 months ago
Ranking refinement and its application to information retrieval
We consider the problem of ranking refinement, i.e., to improve the accuracy of an existing ranking function with a small set of labeled instances. We are, particularly, intereste...
Rong Jin, Hamed Valizadegan, Hang Li