Sciweavers

3507 search results - page 174 / 702
» Slicing for architectural analysis
Sort
View
ANSOFT
1998
140views more  ANSOFT 1998»
15 years 6 months ago
FORM: A Feature-Oriented Reuse Method with Domain-Specific Reference Architectures
Systematic discovery and exploitation of commonality across related software systems is a fundamental technical requirement for achieving successful software reuse. By examining a...
Kyo Chul Kang, Sajoong Kim, Jaejoon Lee, Kijoo Kim...
FAST
2007
15 years 8 months ago
Architectures for Controller Based CDP
Continuous Data Protection (CDP) is a recent storage technology which enables reverting the state of the storage to previous points in time. We propose four alternative architectu...
Guy Laden, Paula Ta-Shma, Eitan Yaffe, Michael Fac...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
15 years 6 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
16 years 1 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
ASPLOS
1989
ACM
15 years 10 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....