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IPPS
2006
IEEE
16 years 19 days ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
ISCA
2006
IEEE
138views Hardware» more  ISCA 2006»
16 years 19 days ago
Learning-Based SMT Processor Resource Distribution via Hill-Climbing
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
Seungryul Choi, Donald Yeung
ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
16 years 19 days ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
16 years 19 days ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen
IV
2006
IEEE
104views Visualization» more  IV 2006»
16 years 19 days ago
Easy Grocery: 3D Visualization in e-Grocery
There are many deficiencies in the traditional electronic commerce schema. The main problem for consideration is the text and picture based design that underpins current HTML syst...
J. Somerville, Liz J. Stuart, N. Barlow
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