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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 3 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
ISPD
2010
ACM
177views Hardware» more  ISPD 2010»
16 years 1 months ago
Skew management of NBTI impacted gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
Ashutosh Chakraborty, David Z. Pan
INFOCOM
2009
IEEE
16 years 1 months ago
Capacity Provisioning a Valiant Load-Balanced Network
—Valiant load balancing (VLB), also called two-stage load balancing, is gaining popularity as a routing scheme that can serve arbitrary traffic matrices. To date, VLB network de...
Andrew R. Curtis, Alejandro López-Ortiz
MICRO
2008
IEEE
88views Hardware» more  MICRO 2008»
16 years 28 days ago
Facelift: Hiding and slowing down aging in multicores
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timi...
Abhishek Tiwari, Josep Torrellas
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
16 years 21 days ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung