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DFT
2005
IEEE
92views VLSI» more  DFT 2005»
16 years 6 days ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
ICTAI
2005
IEEE
16 years 5 days ago
Improving Lotos Simulation Using Constraint Propagation
Lotos is the ISO formal specification language for describing and verifying concurrent and distributed systems. The simulation or execution of complex Lotos specifications is, h...
Malek Mouhoub, Samira Sadaoui
PADS
2005
ACM
16 years 4 days ago
XTW, A Parallel and Distributed Logic Simulator
— In this paper, a new event scheduling mechanism XEQ and a new rollback procedure rb-messages are proposed for use in optimistic logic simulation. We incorporate both of these t...
Qing Xu 0004, Carl Tropper
EUROPAR
2005
Springer
16 years 3 days ago
INSEE: An Interconnection Network Simulation and Evaluation Environment
In this paper we introduce INSEE, an environment to help in the design of interconnection networks for parallel computing systems. It contains two basic modules: a system to genera...
Francisco Javier Ridruejo Perez, José Migue...
PATMOS
2005
Springer
16 years 2 days ago
Efficient Simulation of Power/Ground Networks with Package and Vias
As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the nu...
Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Ta...