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ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
16 years 24 days ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
EVOW
2001
Springer
15 years 11 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
DAC
2006
ACM
15 years 9 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
COMPUTING
2007
101views more  COMPUTING 2007»
15 years 7 months ago
Reverse engineering with subdivision surfaces
Reverse engineering is concerned with the reconstruction of surfaces from three-dimensional point clouds originating from laser-scanned objects. We present an adaptive surface rec...
P. Keller, Martin Bertram, Hans Hagen
TCAD
2011
15 years 2 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...