Sciweavers

4000 search results - page 711 / 800
» Simulation down under
Sort
View
IROS
2009
IEEE
174views Robotics» more  IROS 2009»
16 years 28 days ago
Characterization and modeling of wireless channels for networked robotic and control systems - a comprehensive overview
— The goal of this paper is to serve as a reference for researchers in robotics and control that are interested in realistic modeling, theoretical analysis and simulation of wire...
Yasamin Mostofi, Alejandro Gonzalez-Ruiz, Alireza ...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
16 years 28 days ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
16 years 28 days ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
WINE
2009
Springer
202views Economy» more  WINE 2009»
16 years 26 days ago
A New Ranking Scheme of the GSP Mechanism with Markovian Users
Sponsored search auction is used by most search engines to select ads to display on the web page of a search result, according to advertisers’ bidding prices. The income of this ...
Xiaotie Deng, Jiajin Yu
ARCS
2009
Springer
16 years 26 days ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...