Sciweavers

4000 search results - page 482 / 800
» Simulation down under
Sort
View
ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
16 years 3 months ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 3 months ago
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems
Although several analytical models have been proposed in the literature for different interconnection networks with deterministic routing, very few of them have considered the eff...
Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad
156
Voted
ICCAD
2006
IEEE
130views Hardware» more  ICCAD 2006»
16 years 3 months ago
On bounding the delay of a critical path
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
Leonard Lee, Li-C. Wang
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
16 years 3 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
16 years 3 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...