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FPGA
2003
ACM
120views FPGA» more  FPGA 2003»
16 years 1 days ago
Architecture evaluation for power-efficient FPGAs
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
Fei Li, Deming Chen, Lei He, Jason Cong
HPDC
2000
IEEE
15 years 11 months ago
Evaluation of Task Assignment Policies for Supercomputing Servers: The Case for Load Unbalancing and Fairness
While the MPP is still the most common architecture in supercomputer centers today, a simpler and cheaper machine configuration is growing increasingly common. This alternative s...
Bianca Schroeder, Mor Harchol-Balter
SIGCOMM
1998
ACM
15 years 11 months ago
The MASC/BGMP Architecture for Inter-Domain Multicast Routing
Multicast routing enables e cient data distribution to multiple recipients. However, existing work has concentrated on extending single-domain techniques to wide-area networks, ra...
Satish Kumar, Pavlin Radoslavov, David Thaler, Cen...
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 11 months ago
Software Versus Hardware Shared-Memory Implementation: A Case Study
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, ...
IWRT
2008
15 years 8 months ago
Tag Loss Probability Evaluation for a Continuous Flow of Tags in the EPC-Global Standard
Abstract. This paper addresses the evaluation of a passive RFID system under a continuous flow of tag arrivals and departures, for instance, in a conveyor belt installation. In suc...
Javier Vales-Alonso, M. Victoria Bueno-Delgado, Es...